Install

emerge -av sci-electronics/iverilog

Error吐いた

> cat /var/tmp/portage/sci-electronics/iverilog-10.2/temp/build.log
~~~~
~~~~
~~~~
./main.c: In function ‘main’:
./main.c:450:39: warning: ‘%s’ directive output may be truncated writing up to 4095 bytes into a region of size 4092 [-Wformat-truncation=]
  450 |       snprintf(tmp, sizeof tmp, " -C\"%s\" -- -", iconfig_common_path);
      |                                       ^~          ~~~~~~~~~~~~~~~~~~~
In file included from /usr/include/stdio.h:867,
                 from ./main.c:53:
/usr/include/bits/stdio2.h:67:10: note: ‘__builtin___snprintf_chk’ output between 11 and 4106 bytes into a destination of size 4096
   67 |   return __builtin___snprintf_chk (__s, __n, __USE_FORTIFY_LEVEL - 1,
      |          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   68 |        __bos (__s), __fmt, __va_arg_pack ());
      |        ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
./main.c:323:58: warning: ‘%s’ directive output may be truncated writing up to 4095 bytes into a region of size 4080 [-Wformat-truncation=]
  323 |       snprintf(tmp, sizeof tmp, "%s%civl -V -C\"%s\" -C\"%s\"", base, sep,
      |                                                          ^~
  324 |         iconfig_path, iconfig_common_path);
      |                       ~~~~~~~~~~~~~~~~~~~
In file included from /usr/include/stdio.h:867,
                 from ./main.c:53:
/usr/include/bits/stdio2.h:67:10: note: ‘__builtin___snprintf_chk’ output 18 or more bytes (assuming 4113) into a destination of size 4096
   67 |   return __builtin___snprintf_chk (__s, __n, __USE_FORTIFY_LEVEL - 1,
      |          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   68 |        __bos (__s), __fmt, __va_arg_pack ());
      |        ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
mv cfparse.d dep
mv main.d dep
mv cflexor.d dep
x86_64-pc-linux-gnu-gcc -Wl,-O1 -Wl,--as-needed main.o substit.o cflexor.o cfparse.o -o iverilog
make[1]: Leaving directory '/var/tmp/portage/sci-electronics/iverilog-10.2/work/verilog-10.2/driver'
>>> Source compiled.
>>> Test phase [not enabled]: sci-electronics/iverilog-10.2

>>> Install sci-electronics/iverilog-10.2 into /var/tmp/portage/sci-electronics/iverilog-10.2/image/
make -j5 -j1 DESTDIR=/var/tmp/portage/sci-electronics/iverilog-10.2/image/ install
mv parse.cc.h parse.h 2>/dev/null || mv parse.hh parse.h
mv: cannot stat 'parse.hh': No such file or directory
make: *** [Makefile:259: parse.h] Error 1
 * ERROR: sci-electronics/iverilog-10.2::gentoo failed (install phase):
 *   emake failed
 *
 * If you need support, post the output of `emerge --info '=sci-electronics/iverilog-10.2::gentoo'`,
 * the complete build log and the output of `emerge -pqv '=sci-electronics/iverilog-10.2::gentoo'`.
 * The complete build log is located at '/var/tmp/portage/sci-electronics/iverilog-10.2/temp/build.log'.
 * The ebuild environment file is located at '/var/tmp/portage/sci-electronics/iverilog-10.2/temp/environment'.
 * Working directory: '/var/tmp/portage/sci-electronics/iverilog-10.2/work/verilog-10.2'
 * S: '/var/tmp/portage/sci-electronics/iverilog-10.2/work/verilog-10.2'

iverilogのissueによると,bison3.3.2を使えとのことなので,

emerge -av \=bison-3.3.2

ついでに/etc/portage/package.mask/bison

# For sci-electronics/iverilog-10.2
>sys-devel/bison-3.3.2

を書き込みます. 再度

emerge -av sci-electronics/iverilog-10.2

コンパイル通ったマンになる.

動かしてみる

Ripple-Carry Adder

# RCA.v
module HALF_ADDER(a,b,carry,sum);
   input a,b;
   output carry,sum;
   assign carry = a & b;
   assign sum = a ^ b;
endmodule // HALF_ADDER

module FULL_ADDER(a,b,c_in,c_out,sum);
   input a,b,c_in;
   output c_out,sum;
   wire   w1,w2,w3;
   HALF_ADDER HA1(a,b,w1,w2);
   HALF_ADDER HA2(w2,c_in,w3,sum);
   assign c_out = w1 | w3;
endmodule // FULL_ADDER

module RCA(a,b,ans);
   input [3:0] a,b;
   output [4:0] ans;
   wire [2:0] carry;
   FULL_ADDER FA1(a[0],b[0],1'b0,carry[0],ans[0]);
   FULL_ADDER FA2(a[1],b[1],carry[0],carry[1],ans[1]);
   FULL_ADDER FA3(a[2],b[2],carry[1],carry[2],ans[2]);
   FULL_ADDER FA4(a[3],b[3],carry[2],ans[4],ans[3]);
endmodule // RCA

module RCA_test;
   reg [3:0] a,b;
   wire [4:0] result;
   RCA RCA1(a,b,result);
   initial begin
      a=4'b1101;
      b=4'b0111;
      $monitor("%b+%b=%b(%d+%d=%d)",a,b,result,a,b,result);
   end
endmodule // RCA_test

4bit のRipple-Carry Adder です. Verilog 初めて書くので多分ひどいコードなんでしょうが許してください.

> iverilog RCA.v
> ./a.out
1101+0111=10100(13+ 7=20)

出来てるみたいですね.

Counter

#counter.v
module counter(clk,enable,reset,count);
   input clk,enable,reset;
   output reg [3:0] count;
   always @ (posedge clk) begin
      count <= (reset)? 4'b0000 : count+enable;
   end
endmodule // counter

module counter_test;
   reg clk,enable,reset;
   wire [3:0] count;
   counter counter1(clk,enable,reset,count);
   initial begin
      clk=0;
      enable=0;
      reset=1;
      $dumpfile("counter_test.vcd");
      $dumpvars(0,counter_test);
      $monitor("%t: CLK:%b  ENABLE:%b  RESET:%b  %b",$time,clk,enable,reset,count);
      # 50 $finish;
   end
   always #1
     clk = ~clk;
   always begin
      #1 enable=1;
      #6 enable=0;
   end
   always begin
      #1 reset=1;
      #1 reset=0;
      #30 reset=1;
   end
endmodule // counter_test

本人はenable端子とreset端子のついたCounter のつもりです.

> iverilog counter.v
> ./a.out
VCD info: dumpfile counter_test.vcd opened for output.
                   0: CLK:0  ENABLE:0  RESET:1  xxxx
                   1: CLK:1  ENABLE:1  RESET:1  0000
                   2: CLK:0  ENABLE:1  RESET:0  0000
                   3: CLK:1  ENABLE:1  RESET:0  0001
                   4: CLK:0  ENABLE:1  RESET:0  0001
                   5: CLK:1  ENABLE:1  RESET:0  0010
                   6: CLK:0  ENABLE:1  RESET:0  0010
                   7: CLK:1  ENABLE:0  RESET:0  0010
                   8: CLK:0  ENABLE:1  RESET:0  0010
                   9: CLK:1  ENABLE:1  RESET:0  0011
                  10: CLK:0  ENABLE:1  RESET:0  0011
                  11: CLK:1  ENABLE:1  RESET:0  0100
                  12: CLK:0  ENABLE:1  RESET:0  0100
                  13: CLK:1  ENABLE:1  RESET:0  0101
                  14: CLK:0  ENABLE:0  RESET:0  0101
                  15: CLK:1  ENABLE:1  RESET:0  0110
                  16: CLK:0  ENABLE:1  RESET:0  0110
                  17: CLK:1  ENABLE:1  RESET:0  0111
                  18: CLK:0  ENABLE:1  RESET:0  0111
                  19: CLK:1  ENABLE:1  RESET:0  1000
                  20: CLK:0  ENABLE:1  RESET:0  1000
                  21: CLK:1  ENABLE:0  RESET:0  1000
                  22: CLK:0  ENABLE:1  RESET:0  1000
                  23: CLK:1  ENABLE:1  RESET:0  1001
                  24: CLK:0  ENABLE:1  RESET:0  1001
                  25: CLK:1  ENABLE:1  RESET:0  1010
                  26: CLK:0  ENABLE:1  RESET:0  1010
                  27: CLK:1  ENABLE:1  RESET:0  1011
                  28: CLK:0  ENABLE:0  RESET:0  1011
                  29: CLK:1  ENABLE:1  RESET:0  1100
                  30: CLK:0  ENABLE:1  RESET:0  1100
                  31: CLK:1  ENABLE:1  RESET:0  1101
                  32: CLK:0  ENABLE:1  RESET:1  1101
                  33: CLK:1  ENABLE:1  RESET:1  0000
                  34: CLK:0  ENABLE:1  RESET:0  0000
                  35: CLK:1  ENABLE:0  RESET:0  0000
                  36: CLK:0  ENABLE:1  RESET:0  0000
                  37: CLK:1  ENABLE:1  RESET:0  0001
                  38: CLK:0  ENABLE:1  RESET:0  0001
                  39: CLK:1  ENABLE:1  RESET:0  0010
                  40: CLK:0  ENABLE:1  RESET:0  0010
                  41: CLK:1  ENABLE:1  RESET:0  0011
                  42: CLK:0  ENABLE:0  RESET:0  0011
                  43: CLK:1  ENABLE:1  RESET:0  0100
                  44: CLK:0  ENABLE:1  RESET:0  0100
                  45: CLK:1  ENABLE:1  RESET:0  0101
                  46: CLK:0  ENABLE:1  RESET:0  0101
                  47: CLK:1  ENABLE:1  RESET:0  0110
                  48: CLK:0  ENABLE:1  RESET:0  0110
                  49: CLK:1  ENABLE:0  RESET:0  0110
                  50: CLK:0  ENABLE:1  RESET:0  0110

かなりわかりにくいので,counter_test.vcdを生成してgtkwaveを用いて波形を確認します.

emerge -av gtkwave
> gtkwave counter_test.vcd
image

っぽくなってることが確認できました.